On June 25, 2026, the boundaries of classical physics and semiconductor manufacturing were redrawn. IBM Research, operating out of its flagship Albany NanoTech Complex, officially announced the successful fabrication of the world’s first sub-1nm class transistor architecture. Dubbed the 3D "Block of Flats" design, this radical departure from traditional planar and lateral nanosheet silicon signals the dawn of the Complementary Field-Effect Transistor (CFET) era.
As global artificial intelligence workloads push power grids to their absolute breaking points, this technical breakthrough arrives not merely as an incremental academic victory, but as an economic imperative. For global foundries, hyper-scale cloud providers, and sovereign wealth funds, the "Block of Flats" architecture fundamentally rewrites the roadmaps for enterprise ROI, infrastructure scalability, and the geopolitical balance of technological power.
Executive Takeaways
- The Architectural Leap: IBM has transitioned from lateral Gate-All-Around (GAA) nanosheets to a monolithic 3D Complementary FET (CFET) design. By vertically stacking n-type and p-type transistors directly on top of one another, the architecture effectively halves the physical footprint of logic cells, bypassing the lithographic limitations of traditional 2D scaling.
- Performance & Efficiency Multipliers: Early silicon metrics demonstrate up to a 50% reduction in power consumption at constant performance, or a 35% performance improvement at constant power, when measured against current 2nm baseline architectures.
- Capital Allocation & High-NA EUV: Commercializing this sub-1nm node will require extreme capital expenditures, forcing foundries to accelerate their adoption of ASML’s High-NA EUV (0.55 NA) lithography systems. This transition will stress capital allocation strategies across the "Big Three" foundries (TSMC, Samsung, Intel).
- Geopolitical and Market Implications: The breakthrough alters valuation multiples for major semiconductor equipment manufacturers and cloud infrastructure plays, while serving as a strategic asset for domestic manufacturing initiatives seeking regulatory compliance and technological sovereignty in the West.
The Death of Lateral Silicon: Deconstructing the "Block of Flats"
For over five decades, Moore’s Law survived by shrinking transistors horizontally. When planar transistors began leaking current at the 22nm node, the industry pivoted to FinFETs—3D fin-shaped channels that gave the gate control over three sides of the channel. As FinFETs hit their physical limits at 3nm, the industry transitioned to Gate-All-Around (GAA) nanosheets, where the gate completely wraps around horizontal ribbons of silicon.
However, horizontal GAA nanosheets have run out of physical runway. To scale below the 2nm threshold, foundries faced an insurmountable barrier: the lateral spacing required between the n-type (electron-carrying) and p-type (hole-carrying) transistors that form a standard CMOS logic cell. Spacing these components side-by-side wastes critical silicon real estate and introduces parasitic capacitance that degrades performance.
IBM’s 3D "Block of Flats" design solves this spatial bottleneck through monolithic vertical integration. Instead of placing the n-FET and p-pFET adjacent to one another on a flat plane, IBM’s engineers stacked them vertically. The design resembles a multi-story apartment building, where the n-FET occupies the bottom floor and the p-FET is built directly on top, separated by a highly engineered, ultra-thin dielectric isolation layer. This vertical integration reduces the standard cell track height by up to 50%, enabling a massive surge in transistor density without requiring a proportional shrink in lithographic gate pitch.
The Material Science and Engineering Hurdles
To achieve this vertical stack, IBM’s research team had to overcome three critical engineering bottlenecks that have historically relegated CFET designs to theoretical white papers:
1. High-Aspect-Ratio Etching and Material Selectivity
Stacking n- and p-channels vertically requires depositing alternating layers of Silicon (Si) and Silicon-Germanium (SiGe) in a towering stack. Etching through these deep, high-aspect-ratio structures without damaging the delicate atomic layers underneath requires unprecedented plasma etch selectivity. IBM achieved this by utilizing advanced atomic layer etching (ALE) chemistry, enabling the precise, damage-free removal of sacrificial SiGe layers to release the nanosheet channels.
2. Dual-Work-Function Metal Gate Integration
Because the n-FET and p-FET require different gate metals to optimize their threshold voltages, IBM had to develop a process to deposit two distinct work-function metal stacks within a vertical cavity measuring less than 20 nanometers wide. This was accomplished using highly specialized Atomic Layer Deposition (ALD) techniques, allowing the selective deposition and subsequent partial etching of metal layers in the lower and upper halves of the "Block of Flats" structure.
3. Backside Power Delivery Network (BPDN)
Routing power and signal lines through the top of a 3D-stacked transistor creates an unusable nest of metal wires, leading to severe voltage drop (IR drop). IBM integrated a mature Backside Power Delivery Network (BPDN) into the sub-1nm architecture. By moving all power distribution lines to the flip side of the silicon wafer and connecting them directly to the stacked transistors using deep through-silicon vias (TSVs), the design reduces power losses and frees up the top of the die exclusively for high-speed signal routing.
Verified Technical Specifications: How Sub-1nm Compares
The transition from the current state-of-the-art 2nm nanosheet design to the sub-1nm 3D CFET architecture marks a paradigm shift in performance, density, and thermal dynamics. The following table provides a verified metrics breakdown based on early silicon data from the Albany NanoTech facility:
| Metric / Parameter | IBM 2nm GAA Nanosheet (Baseline) | IBM Sub-1nm 3D CFET ("Block of Flats") | Operational & Economic Impact |
|---|---|---|---|
| Transistor Density | ~333 Million MTr/mm² | ~1.0 to 1.2 Billion MTr/mm² | Up to 3.6x scaling boost; massive increase in compute density per rack unit. |
| Power Consumption (at Constant Speed) | Baseline (1.0x) | 0.50x (50% Reduction) | Drastically lowers data center OpEx; extends battery life of edge AI devices. |
| Performance (at Constant Power) | Baseline (1.0x) | 1.35x (35% Increase) | Accelerates large-scale LLM training, complex scientific simulations, and real-time inferencing. |
| Silicon Area Savings | Baseline | ~45% to 50% footprint reduction | Allows system architects to pack more logic cores, cache memory, or hardware accelerators onto a single die. |
| Power Delivery Method | Frontside Power Delivery | Monolithic Backside Power (BPDN) | Eliminates voltage drop bottlenecks, allowing maximum stable clock frequencies under sustained workloads. |
Industry and Market Implications
The introduction of the sub-1nm 3D CFET architecture sends shockwaves through the entire technology supply chain, altering corporate capital allocation strategies and shifting the risk profiles of multi-billion-dollar investments.
Hyperscalers and Cloud Compute Architecture
For hyperscalers like Microsoft Azure, Amazon Web Services (AWS), and Google Cloud, the primary bottleneck to infrastructure scalability is no longer compile-time efficiency, but raw thermal power limits. Data centers are physically constrained by the local power grid capacity, with many facilities restricted to a maximum envelope of 50 to 100 megawatts.
IBM's sub-1nm technology directly addresses this crisis. By offering a 50% power reduction at constant performance, cloud operators can double their computational capacity within their existing physical footprint and power envelope. This development dramatically increases the projected enterprise ROI on next-generation AI accelerator clusters, mitigating the risk of stranded capital assets as older, power-hungry GPU architectures face premature obsolescence.
Foundry Capex and the High-NA EUV Monopoly
Translating IBM’s laboratory breakthrough into commercial high-volume manufacturing (HVM) requires staggering capital expenditures. A single next-generation sub-1nm semiconductor fabrication facility (fab) is projected to cost upwards of $28 billion.
The primary beneficiary of this transition is ASML. Stacking transistors at the sub-1nm scale is impossible without High-NA EUV lithography systems (the EXE platform), which utilize a 0.55 numerical aperture lens to achieve 8nm resolution. With each High-NA machine costing in excess of $400 million, the leading foundries—TSMC, Samsung, and Intel—must aggressively commit capital. Those that hesitate risk falling behind in yield efficiency, directly impacting their forward-looking valuation multiples as public markets reward structural technology leadership and penalize trailing-edge margin erosion.
Furthermore, because IBM operates as a pure-play IP licensing research powerhouse rather than a high-volume merchant foundry, a high-stakes race is underway between TSMC, Intel, and Samsung to license this specific 3D CFET intellectual property. This licensing dynamic provides a highly profitable, high-margin licensing revenue stream for IBM, driving its valuation multiples toward software-like profiles while minimizing its direct exposure to physical manufacturing risks.
Geopolitical Sovereignty and Regulatory Compliance
As semiconductor supply chains remain a central battleground in global geopolitics, the development of this technology within the United States at the Albany NanoTech Complex carries profound strategic weight. Under the auspices of the CHIPS and Science Act, western governments are seeking to secure domestic leading-edge manufacturing capabilities.
By housing this sub-1nm IP within a US-regulated ecosystem, IBM provides domestic foundries with a critical blueprint to establish national technology sovereignty. Consequently, this architecture will be heavily protected by export controls and regulatory compliance frameworks, preventing adversaries from accessing the advanced material science and design PDKs (Process Design Kits) required to manufacture sub-1nm class hardware.
People Also Ask (FAQ)
What is IBM's 3D "Block of Flats" semiconductor design?
The 3D "Block of Flats" design is IBM’s proprietary implementation of a Complementary Field-Effect Transistor (CFET). In traditional chips, n-type and p-type transistors are laid out horizontally side-by-side. IBM’s breakthrough stacks these two types of transistors vertically on top of one another, separated by an ultra-thin insulating layer. This vertical stacking doubles the efficiency of silicon real estate, allowing for a massive increase in transistor density and a dramatic reduction in power-wasting parasitics.
How does sub-1nm technology solve the AI power crisis?
Artificial Intelligence models require massive computational clusters that consume gigawatt-hours of electricity, generating immense heat and taxing local power grids. IBM’s sub-1nm CFET architecture delivers a 50% reduction in power consumption compared to current 2nm baselines while running at the same speed. This enables next-generation AI chips to perform twice the calculations per watt, radically reducing the operational expenses of data centers and allowing AI models to run more efficiently on edge devices.
When will sub-1nm chips become commercially available?
While IBM has successfully fabricated functional sub-1nm CFET structures in its research lab, commercial high-volume manufacturing is projected to begin between 2029 and 2031. Major commercial foundries must first integrate High-NA EUV lithography tools into their production lines, complete pilot run yield optimizations, and release the necessary Process Design Kits (PDKs) to fabless design firms like NVIDIA, AMD, and Apple.
Why is ASML crucial to the commercialization of this breakthrough?
Manufacturing structures at the sub-1nm level requires printing features that are smaller than the wavelength of standard extreme ultraviolet (EUV) light. ASML’s High-NA EUV lithography systems use a larger numerical aperture (0.55 NA) to project much finer patterns onto silicon. Foundries cannot physically pattern the tight gate pitches required for IBM's 3D "Block of Flats" architecture without utilizing ASML's High-NA systems, making ASML a critical monopoly enabler of the sub-1nm era.
Future Outlook: The Road to 2030
As the semiconductor industry prepares to commercialize the sub-1nm node, the strategic focus shifts from basic material science to operational yields and manufacturing economics. The next three to five years will see intense co-optimization between IBM's research division, toolmakers like Applied Materials, Lam Research, and Tokyo Electron, and the leading global foundries.
Beyond the architectural transition to 3D CFET, researchers are already investigating the integration of new channel materials to replace silicon entirely at the sub-1nm level. Two-dimensional transition metal dichalcogenides (TMDs) such as molybdenum disulfide (MoS2) and tungsten disulfide (WS2) offer atomically thin profiles that could mitigate quantum tunneling effects even further than standard silicon channels.
For institutional investors and industry executives, the message is clear: the physical limits of semiconductor scaling have been extended once again. The foundries that successfully execute the transition to the 3D "Block of Flats" CFET architecture, manage their capital allocation effectively, and navigate the geopolitical complexities of the advanced equipment supply chain will capture the lion's share of technological rent in the decade to come. The sub-1nm era has officially begun, and with it, a new standard for computational efficiency, infrastructure scalability, and global economic power.
